module dmem #(
    parameter DEPTH_WORDS = 256
)(
    input  wire        clk,
    input  wire        memread,
    input  wire        memwrite,
    input  wire [31:0] addr,     // byte address
    input  wire [31:0] wdata,
    output wire [31:0] rdata
);
    reg [31:0] mem [0:DEPTH_WORDS-1];

    // 简化：组合读、同步写
    assign rdata = mem[addr[31:2]];

    always @(posedge clk) begin
        if (memwrite) mem[addr[31:2]] <= wdata;
    end
endmodule

